• DocumentCode
    2162063
  • Title

    Hardware neural network accelerators

  • Author

    Temam, Olivier

  • Author_Institution
    INRIA Saclay, Saclay, France
  • fYear
    2013
  • fDate
    Sept. 29 2013-Oct. 4 2013
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    Because of increasingly stringent energy constraints (e.g., Dark Silicon, there is a growing consensus in the community that we may be moving towards heterogeneous multi-core architectures, composed of a mix of cores and accelerators. Because our community is traditionally focused on general-purpose computing, we have been especially considering accelerator approaches such as GPUs and reconfigurable circuits. An attractive alternative is to investigate accelerators which are focused on a few key algorithms: key algorithms still mean broad application scope, but few algorithms enable energy efficient and cost-effective accelerators.
  • Keywords
    application specific integrated circuits; fault tolerant computing; graphics processing units; learning (artificial intelligence); multiprocessing systems; neural nets; parallel architectures; power aware computing; ASIC; GPU; NN circuit; PARSEC benchmarks; cost-effective accelerators; defect tolerance; energy efficiency; fault tolerance; faulty parts; general-purpose computing; hardware neural network accelerators; heterogeneous multicore architectures; machine-learning techniques; reconfigurable circuits; stochastic algorithms; stringent energy constraints; Artificial neural networks; Biological neural networks; Circuit faults; Communities; Computer architecture; Hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2013 International Conference on
  • Conference_Location
    Montreal, QC
  • Type

    conf

  • DOI
    10.1109/CODES-ISSS.2013.6659008
  • Filename
    6659008