Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS

Author

Skotnicki, T. ; Jurczak, M. ; Martins, J. ; Paoli, M. ; Tormen, B. ; Pantel, R. ; Hernandez, C. ; Campidelli, I. ; Josse, E. ; Ricci, G. ; Galvier, J.

Author_Institution

ST Microelectronics, Crolles, France

fYear

2000

fDate

13-15 June 2000

Firstpage

156

Lastpage

157

Abstract

We propose a new process of selective lateral under-etching of bi-layered Si/SiGe gates, aimed at the formation of well-controlled notches. Weak Ge mole fraction (/spl les/30%) and moderate notch depth render the notch formation compatible with standard CMOS process, and prevent dispersions. The latter, in the case of a shallow notch (/spl les/25 nm) are even smaller than in reference Si-gate devices without a notch. Higher commutation speed, better transconductance and better SGE/DIBL immunity are demonstrated experimentally on notched gate devices.

Keywords

CMOS integrated circuits; Ge-Si alloys; elemental semiconductors; etching; germanium; integrated circuit measurement; semiconductor materials; 25 nm; Ge-SiGe; RF CMOS; SGE/DIBL immunity; bi-layered Si/SiGe gates; commutation speed; high performance CMOS; notch depth; notched gate devices; selective lateral under-etching; selectively under-etched Si/SiGe gates; shallow notch; transconductance; weak Ge mole fraction; well-controlled notches; Capacitance; Chemicals; Etching; Germanium silicon alloys; Implants; Microelectronics; Plasma applications; Radio frequency; Shape; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852807

Filename

852807