Title :
Defect tolerant SRAM based FPGAs
Author :
Kelly, Jason L. ; Ivey, Peter A.
Author_Institution :
Sheffield Univ., UK
Abstract :
We propose a new approach to redundancy for field programmable gate arrays (FPGAs) which uses a novel reconfiguration network. Modifications are made to the wiring segments and a spare element is incorporated at the end of each row. By using the technique it will be possible to construct arrays 10 times larger than are commercially economic at present. The scheme is applicable to any SRAM based FPGA and keeps full software compatability with existing design tools
Keywords :
SRAM chips; application specific integrated circuits; circuit reliability; logic arrays; logic design; logic testing; redundancy; FPGA; SRAM; commercially economic; defect tolerant SRAM; design tools; field programmable gate arrays; reconfiguration network; redundancy; software compatability; wiring segments; Circuits; Decoding; Equations; Field programmable gate arrays; Multichip modules; Random access memory; Routing; Shift registers; Silicon; Switches;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
DOI :
10.1109/ICCD.1994.331955
