Title :
A novel logic compatible gain cell with two transistors and one capacitor
Author :
Ikeda, N. ; Terano, T. ; Moriya, H. ; Emori, T. ; Kobayashi, T.
Author_Institution :
ULSI R&D Labs., Sony Corp., Kanagawa, Japan
Abstract :
Summary form only given. In consumer electronics, cost-effective embedded technology is an important subject. We propose a novel, cost-effective gain cell for memory embedded in logic LSIs. The new cell consists of two conventional bulk transistors and one MOS capacitor. It can be fabricated using the pure logic process with a few additional process steps. The fabrication cost of this cell is lower than that of DRAM or SRAM at a memory density in the 1/spl sim/100 Mbit range.
Keywords :
CMOS logic circuits; CMOS memory circuits; VLSI; integrated circuit technology; large scale integration; 0.25 micron; 1 to 100 Mbit; MOS capacitor; bulk transistors; cost-effective gain cell; fabrication cost; logic LSI embedded memory; logic compatible gain cell; two transistor cell; CMOS logic circuits; Capacitance; Costs; Fabrication; MOS capacitors; MOSFETs; Random access memory; Research and development; Threshold voltage; Ultra large scale integration;
Conference_Titel :
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6305-1
DOI :
10.1109/VLSIT.2000.852812
