Title :
A partially depleted 1.8 V SOI CMOS SRAM technology featuring a 3.77 /spl mu/m/sup 2/ cell
Author :
Cox, K. ; Scott, J. ; Bishop, S. ; Bhat, M. ; Nettleton, B. ; Pan, D. ; Hamilton, M. ; Chang, D. ; Day, L. ; Schani, P.
Author_Institution :
Digital DNA Labs., Motorola Inc., Austin, TX, USA
Abstract :
Summary form only given. A robust 1.8 V partially-depleted SOI SRAM technology has been developed from the 0.20 /spl mu/m bulk CMOS process platform with copper interconnect. The 3.77 /spl mu/m/sup 2/ 6T bitcell features self-aligned local interconnect (SALI) with buried channel PFET (BCPFET) load devices. The technology was used in fabrication of a dense 4 Mb asynchronous SOI SRAM originally designed for bulk Si but modified for SOI fabrication. SOI VLSI die yield equivalent to bulk Si was realized and excellent reliability results were achieved.
Keywords :
CMOS memory circuits; SRAM chips; VLSI; integrated circuit reliability; integrated circuit technology; silicon-on-insulator; 0.2 micron; 1.8 V; 4 Mbit; 6T bitcell; Cu; Cu interconnect; PD-SOI technology; SALI; SOI CMOS SRAM technology; SOI VLSI die yield; Si; asynchronous SOI SRAM; buried channel PFET load devices; partially-depleted SOI SRAM technology; reliability; self-aligned local interconnect; CMOS technology; Copper; Fabrication; Implants; Integrated circuit interconnections; Isolation technology; Random access memory; Space technology; Very large scale integration; Voltage control;
Conference_Titel :
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6305-1
DOI :
10.1109/VLSIT.2000.852813
