Author :
Smeys, P. ; McGahay, V. ; Yang, I. ; Adkisson, J. ; Beyer, K. ; Bula, O. ; Chen, Z. ; Chu, B. ; Culp, J. ; Das, S. ; Eckert, A. ; Hadel, L. ; Hargrove, M. ; Herman, J. ; Lin, L. ; Mann, R. ; Maciejewski, E. ; Narasimha, S. ; O´Neil, P. ; Rauch, S. ; Ryan,
Author_Institution :
Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA
Abstract :
This paper describes a 1.2V high performance 0.13 /spl mu/m generation SOI technology. Aggressive ground-rules and a tungsten damascene local interconnect render the densest 6T SRAM reported to date with a cell area of 2.16 /spl mu/m/sup 2/. This is accomplished with 248nm lithography, using optical proximity correction and resolution enhancement techniques on all critical levels. Interconnect performance requirements are achieved by using up to 8 levels of Cu wiring and an advanced low-k interlevel dielectric.
Keywords :
CMOS memory circuits; SRAM chips; copper; dielectric thin films; integrated circuit interconnections; proximity effect (lithography); silicon-on-insulator; ultraviolet lithography; 0.13 mum; 1.2 V; 248 nm; 6T SRAM; Cu; Cu interconnects; Cu wiring; Si-SiO/sub 2/; advanced low-k interlevel dielectric; cell area; ground-rules; high performance SOI CMOS technology; interconnect performance; lithography; low-k BEOL dielectric; optical proximity correction; resolution enhancement techniques; tungsten damascene local interconnect; CMOS logic circuits; CMOS technology; Delay; Dielectrics; Integrated circuit interconnections; Random access memory; Research and development; Threshold voltage; Tungsten; Wiring;
