ZEPHCAD and FLORA: logic synthesis for control and datapath

We present two logic synthesis systems which have been tuned for different purposes and a new one which is now being developed. The first one, ZEPHCAD, has been tuned for synthesizing control parts in the chip design. ZEPHCAD was developed in 1988. The other, FLORA, has been tuned for synthesizing datapath dominated chip designs. FLORA was developed in 1986. We are developing a new logic synthesis system which unifies the above two. They have been working well so far. However, the size of the LSI chip has been increasing year by year, creating many problems such as in CPU processing time, required memories, timing adjustment, and so on. We are especially preoccupied by the timing adjustment factor. The timing adjustment factor in both the setup and hold constraints of the entire chip is becoming more and more difficult because of the line delay effect. It is in the new logic synthesis system that the timing adjustment problem will be alleviated