A VLSI chip for template matching

We describe the design and implementation of a VLSI chip for image template matching. The hardware algorithm and architecture for template matching are based on a technique known as moment preserving pattern matching. The architecture fully utilizes the principles of parallelism and pipelining in order to obtain high speed and throughput. The proposed VLSI system is much simpler, achieves higher speed, has a lower hardware complexity and utilizes lesser memory than other hardware architectures proposed for template matching in the literature. The architecture was simulated using Verilog HDL. A prototype CMOS VLSI chip implementing the proposed architecture has been designed and verified using the Cadence Opus tools. The chip can process a 512×512 image and 64×64 template in 1.35 msec operating at a frequency of 100 MHz