DocumentCode
2162496
Title
COBRA: an 1.2 million transistor expandable column FFT chip
Author
Sunada, Glen ; Jin, Jain ; Berzins, Matt ; Chen, Tom
Author_Institution
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
fYear
1994
fDate
10-12 Oct 1994
Firstpage
546
Lastpage
550
Abstract
This paper presents an optimized column FFT architecture which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. As a result, the system can compute a 24-bit precision 1 K point complex FFT transform within 9.25 μs, far surpassing the performance of any existing FFT systems
Keywords
digital arithmetic; digital signal processing chips; fast Fourier transforms; signal processing; 1.2 million transistor expandable column FFT chip; 24-bit precision; COBRA chip; bit-serial arithmetic; dynamic reconfiguration; optimized column FFT architecture; Arithmetic; Fast Fourier transforms; Hardware; Parallel processing; Signal processing algorithms; Silicon; Software algorithms; Speech analysis; Switches; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-6565-3
Type
conf
DOI
10.1109/ICCD.1994.331972
Filename
331972
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