Large area defect-tolerant tree architectures

The authors study the problem of designing large-area defect-tolerant tree architectures under the fault model that each processor, switch, and wire may be defective with independent constant probability. Using expander graphs, it is shown that, for any given constant 0<h<1, there is a design of n processors with layout area O(n) such that the harvest rate is asymptotically h, provided the yield of each switch and wire is above a constant threshold depending on h but independent of n. The significance of this result is that, under this fault model, all previous defect-tolerant tree architectures have a harvest rate that is asymptotically 0