A VLSI priority packet queue with overwrite and inheritance

Priority-based flow-control is essential for dead-line based real-time applications. First-in-first-out queues introduce priority inversion, which can cause unbounded delays. Yet very few priority queue implementations exist. This paper presents a novel 1.2 μm CMOS priority packet queue that manipulates its contents in terms of packet segments, rather than individual words. Similar to paged memory, this architecture stores variable-sized packets, while avoiding storage area fragmentation. It significantly increases throughput by distributing the computationally intensive priority comparison operation over the access time for an entire segment. When full, the queue can either perform priority inheritance or overwrite lower priority packets. Its robust handling of a synchronous and disparate read and write clocks makes it suitable for use as a general network interface buffer. Our prototype achieves double the throughput of a conventional design, and larger capacity implementations promise even greater improvements