A partially-depleted SOI compact model - formulation and parameter extraction

Author

Fung, S.K.H. ; Wagner, L. ; Sherony, M. ; Zamdmer, N. ; Sleight, J. ; Michel, M. ; Leobandung, E. ; Lo, S.H. ; Chen, T.C. ; Assaderaghi, F.

Author_Institution

Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA

fYear

2000

fDate

13-15 June 2000

Firstpage

206

Lastpage

207

Abstract

As SOI technology advances into mainstream, an accurate and predictive compact model is necessary to ensure the success of VLSI chip design. This paper describes a compact model which contributes to the successful implementation of the sophisticated 660 MHz 64-bit PowerPC at its first design. This model captures all important SOI specific device characteristics and circuit behavior properly. The parameter extraction methodology, which is essential in achieving a highly accurate model, will be discussed. Verification results using a 0.18 um (1.5 V) high performance SOI CMOS technology will be presented.

Keywords

CMOS digital integrated circuits; VLSI; integrated circuit design; integrated circuit modelling; microprocessor chips; silicon-on-insulator; 0.18 micron; 1.5 V; 64 bit; 660 MHz; PowerPC chip; VLSI design; compact model; parameter extraction; partially depleted SOI CMOS technology; CMOS technology; Impact ionization; Integrated circuit modeling; MOSFET circuits; Parameter extraction; Predictive models; Semiconductor device modeling; Semiconductor diodes; Semiconductor process modeling; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852827

Filename

852827