Title :
A compact FD-SOI MOSFETs fabrication process featuring Si/sub x/Ge/sub 1-x/ gate and damascene-dummy SAC
Author :
Hisamoto, D. ; Kachi, T. ; Tsujikawa, S. ; Miyauchi, A. ; Kusukawa, K. ; Sakuma, N. ; Homma, Y. ; Yokoyama, N. ; Ootsuka, F. ; Onai, T.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
A compact FD-SOI CMOS fabrication process and device structure was demonstrated. A new damascene-dummy SAC process enabled to fabricate reliable contacts with ultra-thin SOI layers. We showed that using in-situ-boron-doped Si/sub x/Ge/sub 1-x/ as a gate material, the adequate threshold voltage of FD-SOI was realized.
Keywords :
Ge-Si alloys; MOSFET; semiconductor materials; silicon-on-insulator; FD-SOI MOSFET; Si/sub x/Ge/sub 1-x/ gate; SiGe; damascene-dummy self-aligned contact; fabrication; threshold voltage; CMOS process; Contact resistance; Etching; Fabrication; Laboratories; MOSFETs; Parasitic capacitance; Threshold voltage; Voltage control; Wafer bonding;
Conference_Titel :
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6305-1
DOI :
10.1109/VLSIT.2000.852828
