AN ultra low power fault tolerant SRAM design in 90nm CMOS

To mitigate the single-event effect, improve the stability and also maintain the low power characteristic of sub-threshold SRAM, a dual interlocked storage cell (DICE) based SRAM cell in 90 nm CMOS technology was proposed to eliminate the drawback of conventional DICE cell during read operation. In order to make the proposed SRAM cell work under different power supply voltages from 0.3 V to 0.6 V, an improved replica sense scheme is applied to produce a reference control signal, with which the optimal read time could be achieved. In this paper, a 256 times 8 bytes SRAM core was simulated and the operating frequency at V_DD=0.3 V is up to 4.7 MHz with power dissipation 6.0 muW, while it is 45.5 MHz at V_DD=0.6 V dissipating 140 muW. The layout of SRAM core was also done in 90 nm CMOS technology.