Performance evaluation of the fixed sequential prefetching on a bus-based multiprocessor: preliminary results

Prefetching caches is an important technique for hiding the average latency of memory accesses by exploiting the overlap of processor computations with data accesses. Several software and hardware-based data prefetching approaches have been proposed. The main benefit of the hardware-based schemes is that they do not need support from the compiler and are transparent to the programmer. Under sequential prefetching, a cache miss causes some number of successive blocks to be prefetched. The number p of blocks following the missing block defines the degree of prefetching. The fixed sequential prefetching is the simplest form of the hardware-based prefetching techniques. In this approach, the degree of prefetching remains constant throughout the execution of the application program. Using a simple model of Petri nets for prefetching, we have obtained some results for fixed sequential prefetching on a bus-based multiprocessor. We change the degree of prefetching from 1 to 9. Our preliminary simulation results show that it is useful when the degree of prefetching has a value on the interval 1-3. Hence, fixed sequential prefetching with degree 3, offers significant performance improvements for bus-based multiprocessors