Title :
Improving CMOS speed at low supply voltages
Author :
Lin, Horng-Dar ; Yan, Ran-Hong ; Yu, Douglas
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
Abstract :
A common approach to reduce CMOS power consumption is to reduce the supply voltage. However, circuit speeds degrade rapidly as the supply voltage drops. This paper uses theoretical analyses and experiments to explore the effectiveness of circuit and process modifications for improving speed at low VDD. In particular, we find that circuits operating in ohmic mode have less speed-VDD sensitivity and thus run faster at low supply voltages
Keywords :
CMOS integrated circuits; circuit analysis computing; power consumption; sensitivity analysis; CMOS speed; low supply voltages; ohmic mode; power consumption; sensitivity; Circuit optimization; Circuit simulation; Circuit testing; Degradation; Energy consumption; Low voltage; Packaging machines; Process control; Propagation delay; Virtual manufacturing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
DOI :
10.1109/ICCD.1994.331990
