Asymptotic limits of video signal processing architectures

Author

Dutta, Santanu ; Wolf, Wayne

Author_Institution

Dept. of Electr. Eng., Princeton Univ., NJ, USA

fYear

1994

fDate

10-12 Oct 1994

Firstpage

622

Lastpage

625

Abstract

This paper investigates the effects of technology scaling on video signal processing (VSP) architectures. We evaluate the processor, the memory, and the interconnect delays using RC models and study how the response times of these logic components scale with feature size. Architectural parameters such as clock skew, clock frequency, memory interleaving, memory efficiency, and average waiting times are analyzed in the light of the scaling behaviors of the above components

Keywords

VLSI; clocks; image processing; memory architecture; signal processing; video signals; RC models; asymptotic limits; average waiting time; clock frequency; clock skew; feature size; interconnect delays; logic components; memory; memory efficiency; memory interleaving; processor; response times; scaling behaviors; technology scaling; video signal processing architectures; Clocks; Delay effects; Equations; Frequency; Interleaved codes; Power system interconnection; Propagation delay; Random access memory; Very large scale integration; Video signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-6565-3

Type

conf

DOI

10.1109/ICCD.1994.331991

Filename

331991