• DocumentCode
    2162921
  • Title

    Implementation of RS decoder based on FPGA in CMMB system

  • Author

    Yang, Xiu-zhi ; Song, Bing ; Wu, Lin-huang

  • Author_Institution
    College of Physics and Information Engineering of Fuzhou University, 350002, China
  • fYear
    2010
  • fDate
    4-6 Dec. 2010
  • Firstpage
    2136
  • Lastpage
    2138
  • Abstract
    This Reed-Solomon(RS) code with perfect error-correcting performance is one of the most important technologies for Mobile Multimedia Transmission. In this paper, Improved Berlekamp-Massey(BM) algorithm is adopted in the research of RS decoder. According to the features of FPGA hardware, Galois field multiplier with constant coefficients is used in implementing RS decoder on FPGA. The hardware complexity of RS decoder is reduced and the decoding speed is enhanced.
  • Keywords
    Computer architecture; Field programmable gate arrays; Galois fields; Iterative decoding; Maximum likelihood decoding; Polynomials; CMMB system; Galois field multiplier; Improved BM algorithm; RS Code;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information Science and Engineering (ICISE), 2010 2nd International Conference on
  • Conference_Location
    Hangzhou, China
  • Print_ISBN
    978-1-4244-7616-9
  • Type

    conf

  • DOI
    10.1109/ICISE.2010.5691820
  • Filename
    5691820
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2162921