Title :
A low jitter dual loop DLL using multiple VCDLs with a duty cycle corrector
Author :
Yeon-Jae Jung ; Seung-Wook Lee ; Daeyun Shim ; Wonchan Kim ; Chang-Hyun Kim ; Soo-In Cho
Author_Institution :
Seoul Nat. Univ., South Korea
Abstract :
A low jitter dual loop DLL with multiple VCDLs has been developed. This DLL whose locking range is 150-600 MHz, allows unlimited phase shift without noise sensitivity issues. A built-in duty cycle corrector guarantees 50% duty cycle under severe transistor mismatch.
Keywords :
CMOS digital integrated circuits; Delay lock loops; Synchronization; Timing circuits; Timing jitter; 0.25 micron; 150 to 600 MHz; 2.5 V; 5 metal digital CMOS technology; 60 mW; clock synchronisation circuitry; duty cycle corrector; low jitter dual loop DLL; multiple VCDLs; phase shift; transistor mismatch; Circuit noise; Clocks; Delay lines; Filters; Interpolation; Jitter; Operational amplifiers; Phase noise; Synchronization; Temperature distribution;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852848
