Title :
A 130 nm generation high density Etox/sup TM/ flash memory technology
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
A 130 nm-generation flash memory technology has been developed, optimized for small cell size, high performance low voltage operation and multi-level-cell and embedded logic capability. Memory cell scaling utilizes the architecture features from the 180 nm technology along with channel erase, advanced 130 nm lithography, dielectric scaling, junction scaling, dual trench and dual spacer technology. 32 Mbit flash memories with a 0.16 um/sup 2/ cell size have been built on this technology showing good yield, performance and reliability.
Keywords :
flash memories; low-power electronics; 130 nm; 32 Mbit; Etox flash memory technology; architecture; channel erase; dielectric scaling; dual spacer; dual trench; embedded logic; junction scaling; lithography; low voltage operation; memory cell scaling; multi-level cell; reliability; yield; Energy management; Flash memory; Implants; Lithography; Logic; Oxidation; Rails; Space technology; Transistors; Voltage;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979398
