DocumentCode :
2163170
Title :
Narrow distribution of threshold voltages in 4 Mbit MONOS memory-cell arrays and its impact on cell operation
Author :
Terano, T. ; Moriya, H. ; Nakamura, A. ; Kosaka, H. ; Hashiguchi, A. ; Nomoto, K. ; Fttjlwara, I. ; Kobayashi, T.
Author_Institution :
Semicond. Network Co., Sony Corp., Kanagawa, Japan
fYear :
2001
fDate :
2-5 Dec. 2001
Abstract :
This paper describes the narrow and non-spread distribution of threshold voltage in MONOS (Metal-oxide-nitride-oxide-semiconductor) memory cell array. We fabricated 4 Mbit MONOS memory test chip using 0.25 /spl mu/m technology. The gate length of the memory cell is shrunk to 0.18 /spl mu/m. The distributions of threshold voltage in many operations are evaluated. As a result range of the distribution of threshold voltage keeps narrow in program and erase operation. It also keeps narrow in heat treatment of 300/spl deg/C. These characteristics are also good advantages of MONOS memory device for multi-bit memory applications. It is also shown that there is a possibility to achieve non-verify operation in both program and erase cycle. The MONOS memory device is a promising form of nonvolatile memory for use in cheaper than floating gate (FG) yet highly reliable embedded applications.
Keywords :
MOS memory circuits; heat treatment; 0.18 micron; 0.25 micron; 300 C; 4 Mbit; MONOS memory cell array; heat treatment; multi-bit memory; nonverify operation; nonvolatile memory; threshold voltage distribution; Electrons; Logic; MONOS devices; Nonvolatile memory; Silicon compounds; Testing; Threshold voltage; Timing; Tunneling; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
Type :
conf
DOI :
10.1109/IEDM.2001.979399
Filename :
979399
Link To Document :
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