On the gate oxide scaling of high performance CMOS transistors

Author

Song, S. ; Kim, H. ; Yoo, J.Y. ; Yi, J.H. ; Kim, W.S. ; Lee, N.I. ; Fujihara, K. ; Kang, H.-K. ; Moon, J.T.

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Gyeonggi, South Korea

fYear

2001

fDate

2-5 Dec. 2001

Abstract

The gate oxide scalability of high performance CMOS transistor has been investigated. In terms of gate leakage, the T/sub ox/ can be scaled down to at least 8 /spl Aring/ with I/sub G/ not exceeding I/sub off/ limit suggested by ITRS. To reduce boron penetration, remote-plasma-nitridation (RPN) oxides were studied. Devices with RPN oxides showed excellent resistance against boron penetration, improved hole mobility, reduced gate leakage, and improved transistor performance. The gate oxide scalability can be extended using the RPN process.

Keywords

CMOS integrated circuits; MOSFET; boron; dielectric thin films; hole mobility; leakage currents; nitridation; 8 A; B penetration reduction; CMOSFET; RPN oxides; Si:B; equivalent oxide thickness; gate leakage; gate oxide scalability; high performance CMOS transistor; hole mobility; remote-plasma-nitridation oxides; Boron; Fabrication; Gate leakage; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFETs; Scalability; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979401

Filename

979401