A full-rate truly monolithic CMOS CDR for low-cost applications

A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6 mum CMOS. The implemented CDR comprises a phase-and frequency-locked loop using an I/Q ring VCO to recover clock from incoming non-return-to-zero (NRZ) data stream and a data decision circuit to retime the received data, respectively. The novelty of this design is that silicon-saving active inductors are used to improve the transmitted bit rate and the compatibility with digital circuits for monolithic integration, to reduce silicon area, while the excessive noise is suppressed by fully differential topology. The tested CDR IC achieves a locking range from 400 MHz to 950 MHz and a RMS jitter of 0.008 UI for a 622 Mb/s pseudorandom bit sequence (PRBS) length of 2³¹-1.