Title :
A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously
Author :
Chen, Dianyong ; Wang, Bo ; Liang, Bangli ; Kwasniewski, Tad
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, ON
Abstract :
This paper presents a 10-Gb/s backplane transmitter with a finite impulse response (FIR) pre-emphasis equalizer to suppress inter-symbol-interference (ISI) at data centers and transition edges simultaneously. The design concepts are discussed. Circuits in 0.13mum IBM CMOS technologies are given. Comparison with conventional data center oriented equalizer and transition edge oriented equalizer are carried out on a 40-inch FR4 differential backplane.
Keywords :
CMOS integrated circuits; FIR filters; equalisers; integrated circuit design; intersymbol interference; IBM CMOS technology; backplane transmitter; bit rate 10 Gbit/s; finite impulse response; intersymbol-interference; preemphasis equalizer; size 0.13 mum; size 40 inch; Backplanes; CMOS technology; Circuits; Clocks; Equalizers; Finite impulse response filter; Intersymbol interference; Jitter; Transceivers; Transmitters; Backplane transmitter; FIR; equalizer; inter-symbol interference; pre-emphasis;
Conference_Titel :
Electrical and Computer Engineering, 2009. CCECE '09. Canadian Conference on
Conference_Location :
St. John´s, NL
Print_ISBN :
978-1-4244-3509-8
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2009.5090318
