Title :
A 1.8 V 18 Mb DDR CMOS SRAM with power reduction techniques
Author :
Kawasumi, A. ; Suzuki, A. ; Hatada, H. ; Takeyama, Y. ; Hirabayashi, O. ; Kameda, Y. ; Hamano, T. ; Otsuka, N.
Author_Institution :
Semicond. Co., Toshiba Corp., Yokohama, Japan
Abstract :
In view of the remarkable progress in MPU performance, improvement in the data rate of L2 cache SRAMs is desirable to maximize system performance. As a solution, Double-Data-Rate (DDR) SRAMs, which can realize an I/O frequency of up to twice that of conventional Single-Data-Rate (SDR) SRAMs, have been reported. Increase in operation-current due to higher operation frequency causes severe power-line noise and heating. Therefore, reduction of operation-current is an important issue in designing high-speed SRAMs. In order to realize both high-frequency operation and power reduction, we propose new sense circuitry and a bit-line load scheme.
Keywords :
CMOS memory circuits; SRAM chips; cache storage; high-speed integrated circuits; low-power electronics; 1.8 V; 18 Mbit; 900 MHz; DDR CMOS SRAM; HF operation; L2 cache SRAMs; bit-line load scheme; data rate improvement; double-data-rate SRAM; heating; high-speed SRAMs; operation frequency; operation-current; power reduction techniques; power-line noise; sense circuitry; static RAM; Capacitance; Circuit noise; Delay; Heating; Packaging; Random access memory; Read-write memory; Semiconductor device noise; System performance; Timing;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852855
