Title :
A 256-Mb Double-Data-Rate SDRAM with a 10-mW Analog DLL Circuit
Abstract :
The developed 256-Mb double-data-rate (DDR) SDRAM employs a one-cycle stage-selection analog DLL (delayed-locked loop) circuit-running at IO mW with a 20-ps jitter and a 65- cycles lock-in - and a fully differential clocking system to provide 2~ 0.33-ns clock-to-data-output delay, 0.06-ns setup time and 0.26-ns hold time with respect to the data strobe. This performance represents the possibility of over 250-MHz (500 Mb/s/pin) operation. An even/odd-shared redundancy circuit for a 2-b prefetch reduces the number of fuses by 33%.
Keywords :
MMIC; UHF integrated circuits; analog integrated circuits; application specific integrated circuits; binary decision diagrams; digital signal processing chips; formal verification; high level synthesis; industrial property; integrated circuit interconnections; integrated circuit layout; integrated circuit testing; low-power electronics; microprocessor chips; mixed analog-digital integrated circuits; network routing; reconfigurable architectures; timing; BDD-based model checking; DSPs; IP protection; RF circuits; SOCs; debugging methodologies; embedded software; floorplanning; formal verification; global routing; high-level synthesis; interconnect modelling; low-power design; microprocessors; mixed-signal design; power estimation; power grid analysis; reconfigurable systems; signal integrity; test generation; timing analysis; Jitter; Phased locked loop; SDRAM;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852856
