Title :
Design for testability: tunnelling through the test wall
Author :
Maxwell, Peter C.
Author_Institution :
Integrated Circuit Business Div., Hewlett-Packard Co., Palo Alto, CA, USA
Abstract :
This paper discusses design for testability as a means of ensuring that high quality tests can be generated for an IC in reasonable time by avoiding the “over the wall” mentality. A discussion on fault models is followed by general benefits of DFT. Scan design is then described in some detail, together with general DFT guidelines, including representative design rules which must be followed. Some cost/benefit tradeoffs are considered, and the paper concludes by discussing various required components of a composite test suite
Keywords :
automatic testing; design for testability; fault diagnosis; integrated circuit design; integrated circuit testing; logic design; logic testing; production testing; DFT; IC testing; composite test suite; design for testability; fault models; high quality tests; scan design; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Delay; Design for testability; Fault detection; Semiconductor device modeling; System testing; Tunneling;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606613
