DocumentCode
2163486
Title
Yield evaluation of WSI parallel systems
Author
Tzeng, Nian-Feng ; Chen, Chung-Han
Author_Institution
Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
fYear
1991
fDate
29-31 Jan 1991
Firstpage
156
Lastpage
162
Abstract
The authors propose a methodology for estimating the yield of WSI (wafer scale integration) parallel systems efficiently and accurately by taking advantage of the fact that most of the parallel systems have recursive structures by nature. This methodology evaluates yield by means of a recursive approach without enumerating all fixable states. It is often possible to derive the yield of WSI parallel systems (with recursive structures) of any size. Using this approach, the authors evaluate the exact yield of a fault-tolerant modular binary tree and the yield bounds of a reconfigurable cube-connected cycle structure
Keywords
VLSI; fault tolerant computing; hypercube networks; parallel architectures; trees (mathematics); WSI parallel systems; fault-tolerant modular binary tree; reconfigurable cube-connected cycle structure; recursive approach; recursive structures; wafer scale integration; yield; Computer aided manufacturing; Costs; Production; Recursive estimation; Redundancy; Switches; Topology; Virtual manufacturing; Wafer scale integration; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9126-3
Type
conf
DOI
10.1109/ICWSI.1991.151710
Filename
151710
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