DocumentCode
2163514
Title
Overview of SHDSL system performance
Author
Daecke, D.
Author_Institution
Infineon Technol. AG, Munich, Germany
fYear
2001
fDate
10-11 Sept. 2001
Firstpage
2
Lastpage
6
Abstract
SHDSL is the first standardized multi-bit-rate symmetric DSL for data rates between 192 kbit/s and 2312 kbit/s. A 16-level trellis-coded PAM line code is used. The main challenges of SHDSL system design are optimization with respect to reach, spectral compatibility, power consumption and implementation cost. The loop reach of PAM-based DSL systems can be estimated by a method independent of specific implementation details. In this paper, techniques to increase loop reach using shaped and asymmetric PSD are discussed. With asymmetric PSD, some increase in loop reach can be obtained if ideal assumptions are made on the system. but in application this theoretical increase is limited by practical implementation issues, and is counter-balanced by higher power consumption.
Keywords
channel coding; data communication; digital subscriber lines; power consumption; pulse amplitude modulation; trellis coded modulation; SHDSL; asymmetric PSD; data rates; implementation cost; loop reach; multi-bitrate symmetric DSL; power consumption; power spectral density; pulse amplitude modulation; reach optimization; shaped PSD; spectral compatibility; system design; trellis-coded PAM; DSL; Delay; Energy consumption; Europe; Frequency; ISDN; Pulse modulation; System performance; Telecommunication standards; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
BroadBand Communications for the Internet Era Symposium digest, 2001 IEEE Emerging Technologies Symposium on
Conference_Location
Richardson, TX, USA
Print_ISBN
0-7803-7161-5
Type
conf
DOI
10.1109/ETS.2001.979409
Filename
979409
Link To Document