A DDR/SDR-compatible SDRAM design with a three-size flexible column redundancy

Author

Sakata, T. ; Morita, S. ; Nagashima, O. ; Noda, H. ; Takahashi, T. ; Sonoda, T. ; Tadokoro, H. ; Ichikawa, H. ; Adou, T. ; Hanzawa, S. ; Ohi, M. ; Ookuma, S. ; Suzuki, Y. ; Tanaka, H. ; Ishii, K.

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

2000

fDate

15-17 June 2000

Firstpage

116

Lastpage

119

Abstract

Two circuit techniques are proposed to design a SDRAM which operates both at a double-data-rate (DDR) and a single-data-rate (SDR). The common/separated I/O scheme enables 2-bit prefetching under a DDR and interrupt operations under an SDR with half the number of data-bus lines otherwise needed. The SSTL/LVTTL-compatible input buffer allows a narrow setup/hold time. Furthermore, the three-size flexible column redundancy enhances the yield. To evaluate these techniques, a 256-Mb SDRAM has been designed assuming 0.16-/spl mu/m technology and simulated with 167-MHz operations.

Keywords

CMOS memory circuits; DRAM chips; High-speed integrated circuits; Integrated circuit reliability; Redundancy; 0.16 micron; 167 MHz; 256 Mbit; DDR/SDR-compatible SDRAM design; SSTL/LVTTL-compatible input buffer; common/separated I/O scheme; double-data-rate; interrupt operations; single-data-rate; synchronous DRAM; three-size flexible column redundancy; Bandwidth; Circuit simulation; DRAM chips; Frequency; Laboratories; Prefetching; Random access memory; SDRAM; Time factors; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6309-4

Type

conf

DOI

10.1109/VLSIC.2000.852866

Filename

852866