Title :
Optimized integrated copper gap-fill approaches for 2x flash devices
Author :
Ma, Paul ; Luo, Qian ; Sundarrajan, Arvind ; Lu, Jiang ; Aubuchon, Joseph ; Tseng, Jennifer ; Kumar, Niranjan ; Okazaki, Motoya ; Wang, Yuchun ; Wang, You ; Chen, Yufei ; Naik, Mehul ; Emesh, Ismail ; Narasimhan, Murali
Author_Institution :
Appl. Mater. Inc., Santa Clara, CA
Abstract :
Physical vapor deposited (PVD) Cu seed layers have been successfully implemented for Cu gap-fill in feature sizes for the 2x nm flash devices. By tuning the incident angle of the incoming flux of Cu ions as well as utilizing the resputtering parameter, the overhang, sidewall coverage and asymmetry can be well controlled to enable complete fill by subsequent electrochemical deposition (ECD). Chemical vapor deposition (CVD) Cobalt (Co) films were also investigated as an enhancement layer for Cu gap-fill. It was observed that the insertion of a 1.5nm-thick CVD Co layer, deposited between a PVD Ta barrier and a Cu seed layer could effectively enhance gap-fill in the small geometry trench/via structures. The CVD Co enhancement layer could also significantly improve the electromigration (EM) resistance of the Cu interconnects. The Chemical Mechanical Polish (CMP) process was also developed to provide an integrated solution.
Keywords :
chemical mechanical polishing; chemical vapour deposition; cobalt; copper; electrodeposition; electromigration; flash memories; integrated circuit interconnections; metallic thin films; tantalum; 2x flash devices; CMP; CVD; Cu interconnects; Cu ions; Cu seed layers; Cu-Ta-Co; chemical mechanical polish process; chemical vapor deposition; cobalt films; electrochemical deposition; electromigration resistance; integrated copper gap-fill; physical vapor deposition; resputtering parameter; size 1.5 nm; trench/via structures; Atherosclerosis; Chemical vapor deposition; Copper; Electromigration; Inductors; Integrated circuit interconnections; Metallization; Plasma chemistry; Plasma properties; Plasma temperature;
Conference_Titel :
Interconnect Technology Conference, 2009. IITC 2009. IEEE International
Conference_Location :
Sapporo, Hokkaido
Print_ISBN :
978-1-4244-4492-2
Electronic_ISBN :
978-1-4244-4493-9
DOI :
10.1109/IITC.2009.5090334