DocumentCode :
2163738
Title :
Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers
Author :
Sidiropoulos, S. ; Dean Liu ; Jaeha Kim ; Guyeon Wei ; Horowitz, M.
Author_Institution :
Rambus Inc., Mountain View, CA, USA
fYear :
2000
fDate :
15-17 June 2000
Firstpage :
124
Lastpage :
127
Abstract :
A technique for designing DLLs and PLLs using CMOS buffers with a regulated supply is presented. By scaling the charge pump current and the output resistance of the regulating amplifier, the proposed loops achieve a wide bandwidth that tracks the operating frequency, a constant damping factor, large operating range and low noise sensitivity. Prototype loops designed in 0.35-/spl mu/m CMOS processes exhibit >10x operating range and less than 1% input tracking jitter.
Keywords :
Adaptive systems; Buffer circuits; CMOS integrated circuits; Delay lock loops; Phase locked loops; 0.35 micron; CMOS processes; adaptive bandwidth DLLs; adaptive bandwidth PLLs; charge pump current scaling; constant damping factor; large operating range; low noise sensitivity; output resistance scaling; regulated supply CMOS buffers; regulating amplifier; Bandwidth; Delay; Frequency; Integrated circuit noise; Phase locked loops; Regulators; Tracking loops; Virtual colonoscopy; Voltage control; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
Type :
conf
DOI :
10.1109/VLSIC.2000.852868
Filename :
852868
Link To Document :
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