Title :
Co-design of reliable signal and power interconnects in 3D stacked ICs
Author :
Lee, Young-Joon ; Healy, Mike ; Lim, Sung Kyu
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
Abstract :
With the rapid advance of die stacking and through-silicon-via fabrication technologies, the era of 3D ICs is near. Yet, the knowledge base of 3D IC design techniques is still not matured enough. In this paper, we investigate the design issues raised during the system-level integration of signal and power interconnects in 3D ICs. Routing congestion and power noise are analyzed, and various factors that affect performance and reliability metrics are identified.
Keywords :
integrated circuit design; integrated circuit interconnections; integrated circuit manufacture; integrated circuit reliability; 3D stacked IC; die stacking; power interconnects; reliability metrics; reliable signal; system-level integration; through-silicon-via fabrication technologies; Fabrication; Integrated circuit noise; Packaging; Performance analysis; Power system interconnection; Power system reliability; Routing; Three-dimensional integrated circuits; Through-silicon vias; Wires;
Conference_Titel :
Interconnect Technology Conference, 2009. IITC 2009. IEEE International
Conference_Location :
Sapporo, Hokkaido
Print_ISBN :
978-1-4244-4492-2
Electronic_ISBN :
978-1-4244-4493-9
DOI :
10.1109/IITC.2009.5090339
