A reconfigurable integrated circuit for high performance computer arithmetic

Author

Miller, NL ; Quigley, SF

Author_Institution

Sch. of Electron. & Electr. Eng., Birmingham Univ., UK

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

161

Abstract

In this paper, we present the design of a novel Field Programmable Gate Array (FPGA) which contains the necessary logic elements to support high performance computer arithmetic. The FPGA contains a routing framework and logic cell structure that is suitable for implementing digital systems for computer arithmetic, image processing, digital signal processing and similar computationally intensive applications. The proposed architecture is flexible, reconfigurable and will support operands of various sizes for fixed point parallel and serial binary computations

Keywords

digital arithmetic; field programmable gate arrays; reconfigurable architectures; computer arithmetic; digital signal processing; digital system; field programmable gate array; fixed point binary computation; image processing; integrated circuit; logic element; parallel computation; reconfigurable architecture; reconfigurable arithmetic FPGA; serial computation; Digital arithmetic; Digital signal processing; Digital systems; Field programmable gate arrays; High performance computing; Image processing; Logic design; Programmable logic arrays; Reconfigurable logic; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706866

Filename

706866