VHDL-based design and analysis of defect tolerant VLSI/WSI array architectures

Presents an integrated computer-aided design environment, the VAR (VHDL-based array reconfiguration) system, for the design, diagnosis, reconfiguration, simulation, and evaluation of an array architecture described in VHDL. VAR allows one to study fault diagnosis and reconfiguration algorithms by inserting user-defined faults into the array and then locating the faulty processing elements as well as simulating the actual reconfiguration process by mapping a target array onto a host array. Thus, VAR can assist the designer in evaluating different combinations of diagnosis algorithms, reconfiguration algorithms, and reconfigurable architectures