Title :
A 10-Gb/s CMOS clock and data recovery circuit
Author :
Savoj, J. ; Razavi, B.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
A 10-Gb/s phase-locked clock and data recovery circuit incorporates a 5-GHz interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-/spl mu/m CMOS technology, the circuit exhibits an rms jitter of 6.6 ps in the recovered clock with random data input of length 2/sup 23/-1. The power dissipation is 99 mW from a 2.6-V supply.
Keywords :
CMOS digital integrated circuits; Clocks; Digital phase locked loops; Microwave integrated circuits; Optical communication equipment; Optical fiber communication; Phase detectors; Synchronization; Timing circuits; Timing jitter; 0.18 micron; 2.6 V; 99 mW; CMOS technology; clock recovery circuit; data recovery circuit; demultiplexing; half-rate phase detector; interpolating voltage-controlled oscillator; linear characteristic; phase-locked circuit; power dissipation; recovered clock; rms jitter; CMOS technology; Charge pumps; Circuits; Clocks; Delay; Detectors; Frequency; Jitter; Phase detection; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852871
