Title :
A 50-mW 14-bit 2.5-MS/s /spl Sigma/-/spl Delta/ modulator in a 0.25 /spl mu/m digital CMOS technology
Author :
Balmelli, P. ; Qiuting Huang ; Piazza, F.
Author_Institution :
Integrated Syst. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland
Abstract :
A 5/sup th/-order single-loop /spl Sigma/-/spl Delta/ modulator has been implemented in a 0.25 /spl mu/m digital CMOS process, where the supply voltage is only 2.5 V and the capacitor option is not available. A tri-level quantizer is used to improve loop stability. The sampling frequency of the modulator is 80 MHz and the oversampling ratio is 32. Measured over a 1 MHz signal bandwidth, dynamic range is 86 dB, peak SNR is 80 dB and peak SNDR is 78 dB. The modulator consumes only 50 mW.
Keywords :
CMOS digital integrated circuits; Circuit stability; Sigma-delta modulation; /spl Sigma/-/spl Delta/ modulator; 0.25 micron; 14 bit; 2.5 V; 50 mW; 80 MHz; digital CMOS technology; dynamic range; loop stability; oversampling ratio; sampling frequency; tri-level quantizer; Bandwidth; CMOS technology; Capacitors; Circuits; Delta modulation; Digital modulation; Frequency; Low-frequency noise; Noise shaping; Signal to noise ratio;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852873
