Title :
Reliable through silicon vias for 3D silicon applications
Author :
Shapiro, M. ; Interrante, M. ; Andry, P. ; Dang, B. ; Tsang, C. ; Liptak, R. ; Griffith, J. ; Sprogis, E. ; Guerin, L. ; Truong, V. ; Berger, D. ; Knickerbocker, J.
Author_Institution :
IBM Microelectron., Austin, TX
Abstract :
The use of through silicon vias (TSVs) is required to implement 3D chip stacking technology. This work explores a method to fabricate highly reliable TSVs that is compatible with CMOS processing. The key feature of the TSVs is a redundant tungsten bar with a high temperature thermal oxide insulating liner. Care must be taken when exposing the TSVs from the back side so that material is not left on the surface that can cause a leakage path to the silicon wafer. TSVs were produced with that had no fails through standard JDEC testing.
Keywords :
CMOS integrated circuits; high-temperature electronics; integrated circuit reliability; 3D chip stacking technology; 3D silicon applications; CMOS processing; high temperature thermal oxide insulating liner; silicon wafer; through silicon vias; Bandwidth; CMOS technology; Microelectronics; Packaging; Power system reliability; Rivers; Silicon; Stacking; Testing; Wiring;
Conference_Titel :
Interconnect Technology Conference, 2009. IITC 2009. IEEE International
Conference_Location :
Sapporo, Hokkaido
Print_ISBN :
978-1-4244-4492-2
Electronic_ISBN :
978-1-4244-4493-9
DOI :
10.1109/IITC.2009.5090341
