The ballistic FET: design, capacitance and speed limit

Author

Solomon, P.M. ; Laux, S.E.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2001

fDate

2-5 Dec. 2001

Abstract

In this paper we present a design methodology for the ballistic FET (BFET) which illuminates many topics currently under discussion such as the injection velocity, the role of the contacts, and the meaning of the capacitance and mobility. Both InGaAs/InAlAs in the 20-30 nm gate length range, and Si/SiO/sub 2/ FETs in the 10-20 nm range are simulated using Monte Carlo techniques, where the InGaAs FETs are almost purely ballistic, whereas the Si FETs were not. Expressions for the BFET drain current are derived in the extreme quantum limit and for zero thickness gate insulator, where the importance of the degeneracy capacitance is emphasized. An ultimate speed limit for the BFET is derived.

Keywords

Monte Carlo methods; capacitance; carrier mobility; high field effects; insulated gate field effect transistors; semiconductor device models; 10 to 30 nm; BFET capacitance; BFET drain current; InGaAs-InAlAs; Monte Carlo techniques; Si-SiO/sub 2/; ballistic FET; contacts; degeneracy capacitance; design methodology; injection velocity; mobility; speed limit; zero thickness gate insulator; Ballistic transport; Capacitance; Double-gate FETs; Indium compounds; Indium gallium arsenide; Insulation; Silicon; Stationary state; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979425

Filename

979425