Title :
Design criteria for a fully depleted-0.1 μm SOI technology
Author :
Burns, J.A. ; Frankel, R.S. ; Soares, A.M. ; Wyatt, P.W.
Author_Institution :
Lincoln Lab., MIT, Lexington, MA, USA
Abstract :
A sub-0.25 μm fully depleted silicon-on-insulator (FDSOI) technology has been developed and fully scaled ring oscillators fabricated using 193-nm lithography. This technology is being extended by incorporating phase shift techniques with 193-nm lithography to fabricate polysilicon gates with 0.1 μm drawn channel lengths. The purpose of this paper is to define the process and design requirements for a fully depleted, 0.1 μm SOI technology and predict the performance characteristics of 0.1 μm ring oscillators
Keywords :
CMOS digital integrated circuits; doping profiles; elemental semiconductors; integrated circuit design; lithography; silicon; silicon-on-insulator; 0.1 micron; 193 nm; Si; channel lengths; fully depleted silicon-on-insulator technology; fully scaled ring oscillators; performance characteristics; phase shift techniques; polysilicon gates; Analytical models; Boron; Data mining; Delay; Design for experiments; Doping; Implants; Ring oscillators; Space technology; Threshold voltage;
Conference_Titel :
SOI Conference, 1997. Proceedings., 1997 IEEE International
Conference_Location :
Fish Camp, CA
Print_ISBN :
0-7803-3938-X
DOI :
10.1109/SOI.1997.634941
