Title :
A clock distribution network for microprocessors
Author :
Restle, P.J. ; McNamara, T.G. ; Webber, D.A. ; Camporese, P.J. ; Eng, K.F. ; Jenkins, K.A. ; Allen, D.H. ; Rohn, M.J. ; Quaranta, M.P. ; Boerstler, D.W. ; Alpert, C.J. ; Carter, C.A. ; Bailey, R.N. ; Petrovic, J.G. ; Krauter, B.L. ; McCredie, B.D.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
A global clock distribution strategy implemented on several microprocessor chips is described. The clock network consists of buffered, tunable tree networks, with the final trees all driving a common grid. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune a single interconnect network with 6 m of wire and 50,000 resistors, capacitors, and inductors. Global clock skew as low as 22 ps was measured for large microprocessor chips.
Keywords :
Clocks; Integrated circuit design; Integrated circuit interconnections; Integrated circuit measurement; Microprocessor chips; VLSI; 22 ps; clock distribution network; clock skew; common grid; global clock distribution strategy; microprocessor chips; single interconnect network; tunable tree networks; tuning method; Clocks; Distribution strategy; Frequency; Microprocessor chips; Network topology; Testing; Tunable circuits and devices; Tuning; Uncertainty; Wire;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852885
