Title :
DFT for embedded charge-pump PLL systems incorporating IEEE 1149.1
Author :
Goteti, Prashant ; Devarayanadurg, Giri ; Soma, Mani
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
In this work we present a DFT strategy to test embedded Charge-Pump Phase Locked Loops (CP-PLL) in systems incorporating boundary scan, wherein the proposed DFT allows the verification of the operating frequency range of the CP-PLL while the system is in test mode. This is achieved with a minimal degradation in PLL performance, with lock characteristics remaining unchanged. Simulation results with the layout extracted netlist of the CP-PLL are used to illustrate the working of the technique
Keywords :
CMOS integrated circuits; IEEE standards; boundary scan testing; design for testability; integrated circuit testing; mixed analogue-digital integrated circuits; phase locked loops; DFT strategy; IEEE 1149.1; boundary scan; embedded charge-pump PLL systems; layout extracted netlist; operating frequency range verification; Charge pumps; Circuit testing; Clocks; Degradation; Design for testability; Feedback circuits; Frequency; Phase locked loops; System testing; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606615
