Title :
1 GHz leading zero anticipator using independent sign-bit determination logic
Author :
Lee, K.T. ; Nowka, K.J.
Author_Institution :
IBM Austin Res. Lab., TX, USA
Abstract :
The architecture and design methodology of a leading zero anticipator (LZA) using built-in sign-bit determination logic are described. The LZA was implemented in the 1 GHz floating point unit using a 1.8 V, 0.12/0.15(n/p)/spl mu/m L/sub eff/ IBM CMOS technology. The design shows 730 ps of latency and operates at 1 GHz with 5 levels of delayed reset dynamic circuit logic. With the LZA the sign-bit is determined in 446 ps with an area overhead of 8%, whereas a conventional adder generates the sign-bit in 770 ps.
Keywords :
Adders; CMOS digital integrated circuits; Floating point arithmetic; Microprocessor chips; VLSI; 0.12 micron; 1 GHz; 1.15 micron; 1.8 V; 446 ps; 730 ps; IBM CMOS technology; area overhead; delayed reset dynamic circuit logic; design methodology; floating point unit; independent sign-bit determination logic; latency; leading zero anticipator; microprocessors; sign-bit generation; Bismuth; Delay; Equations; Hardware; Logic circuits; Logic design; Logic devices; Marine vehicles; Signal generators; Timing;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852888
