VLSI implementation of dynamically reconfigurable hardware-based cryptosystem

Author

Mitsuyama, Y. ; Andales, Z. ; Onoye, T. ; Shirakawa, I.

Author_Institution

Dept. of Inf. Syst. Eng., Osaka Univ., Japan

fYear

2000

fDate

15-17 June 2000

Firstpage

204

Lastpage

205

Abstract

A cipher core has been implemented, which is dedicated to the 64-bit block, 128-bit key novel hardware-based cryptosystem called Chameleon. Chameleon adopts the approach that is distinctive for its two 32-cell, 8-context dynamically reconfigurable unit to generate subkeys for each of the 16 iterations of encryption process. The proposed cipher core has been integrated in the die area of 5.90 mm/sup 2/ by means of a 0.6 /spl mu/m CMOS 3 LM technology which attains a maximum throughput of 635 Mbps.

Keywords

CMOS digital integrated circuits; Cryptography; Digital signal processing chips; Reconfigurable architectures; VLSI; 0.6 micron; 128 bit; 178.6 MHz; 635 Mbit/s; 64 bit; CMOS 3 LM technology; Chameleon system; DSP chip; VLSI implementation; cipher core implementation; dynamically reconfigurable hardware-based cryptosystem; encryption process; subkeys generation; CMOS technology; Circuits; Cryptography; Engines; Hardware; Information systems; Reconfigurable logic; Software algorithms; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6309-4

Type

conf

DOI

10.1109/VLSIC.2000.852891

Filename

852891