Title :
An 8-bit 125 MS/s CMOS folding ADC for Gigabit Ethernet LSI
Author :
Kwangho Yoon ; Jeongho Lee ; Deog-Kyoon Jeong ; Wonchan Kim
Author_Institution :
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
Abstract :
An 8-bit 125 MS/s CMOS folding ADC using an equalizing technique is presented, which reduces the settling time of the analog folding processor to obtain a higher sampling rate. The prototype chip, fabricated in a 0.35 /spl mu/m triple metal digital CMOS process, occupies an area of 0.8 mm/sup 2/ and consumes 110 mW achieving 6.4 effective bits for a Nyquist input signal.
Keywords :
Analog-digital conversion; CMOS integrated circuits; Data communication equipment; High-speed integrated circuits; Large scale integration; Local area networks; 0.35 micron; 110 mW; 8 bit; CMOS folding ADC; Gigabit Ethernet LSI; Nyquist input signal; analog folding processor; equalizing technique; sampling rate improvement; settling time reduction; triple metal digital CMOS process; CMOS process; Capacitance; Circuits; Communication channels; Energy consumption; Ethernet networks; Large scale integration; Signal processing; Signal sampling; Voltage;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852893
