DocumentCode
2164267
Title
A 1.6 ns access, 1 GHz two-way set-predicted and sum-indexed 64-kByte data cache
Author
Silberman, J. ; Aoki, N. ; Kojima, N. ; Sang Dhong
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
2000
fDate
15-17 June 2000
Firstpage
220
Lastpage
221
Abstract
A 64-kByte cache exploits combined address generation and word line decoding in the SRAM array, translation array, and directory. In place of a late select, set selection in the two-way associative cache is accomplished in the decode path by accessing a stored prediction from a sum-indexed array built into the decoder.
Keywords
CMOS memory circuits; Cache storage; Content-addressable storage; Decoding; 0.22 micron; 1 GHz; 1.6 ns; 64 kByte; SRAM array; associative cache; combined address generation/word line decoding; decoder; directory; set selection; stored prediction; sum-indexed array; sum-indexed data cache; translation array; two-way set-predicted data cache; Adders; Decoding; Delay; Frequency; Hardware; Laboratories; Logic arrays; Random access memory; Reduced instruction set computing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-6309-4
Type
conf
DOI
10.1109/VLSIC.2000.852896
Filename
852896
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