Title :
A very low power channel select filter for IS-95 CDMA receiver with on-chip tuning
Author :
Kuo, T.C. ; Lusignan, B.B.
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
Abstract :
A channel-select filter with on-chip PLL tuning for CDMA IS-95 has been integrated in a 0.35-/spl mu/m digital CMOS technology. To achieve both low power and robustness, dynamic range scaling is implemented on an elliptic ladder prototype. The dynamic range scaling is based on the special requirement for the wireless receiver. A new method to analyze the trade-off between filter noise and power consumption is presented. The filter and PLL dissipate 2.9 mW and 1.6 mW from a 3-V supply, and the die area is 1.06 mm/sup 2/. The filter achieves 61 dB stopband rejection, 0.05 dB/0.2/spl deg/ I/Q gain/phase mismatch, 100 /spl mu/Vrms input-referred noise, 20 dBm IIP3, and 58 dB SFDR.
Keywords :
CMOS analog integrated circuits; Cellular radio; Circuit tuning; Code division multiple access; Integrated circuit noise; Low-power electronics; Phase locked loops; UHF filters; UHF integrated circuits; 0.35 micron; 1.6 mW; 2.9 mW; 3 V; CMOS technology; I/Q gain/phase mismatch; IS-95 CDMA receiver; PLL tuning; channel select filter; die area; dynamic range scaling; elliptic ladder prototype; filter noise; input-referred noise; on-chip tuning; power consumption; robustness; stopband rejection; CMOS technology; Digital filters; Dynamic range; Energy consumption; Multiaccess communication; Noise robustness; Phase locked loops; Phase noise; Power filters; Prototypes;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852903
