DocumentCode
2164431
Title
On chip monitoring of via degradation
Author
Ahmed, Fahad ; Milor, Linda
Author_Institution
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
fYear
2009
fDate
1-3 June 2009
Firstpage
137
Lastpage
139
Abstract
The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.
Keywords
integrated circuit design; microprocessor chips; reliability; chip monitoring; degradation; failure distribution parameters; path length; Bonding processes; Degradation; Gold; Micromechanical devices; Monitoring; Oxidation; Silicon; Testing; Thermal stresses; Wafer bonding;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference, 2009. IITC 2009. IEEE International
Conference_Location
Sapporo, Hokkaido
Print_ISBN
978-1-4244-4492-2
Electronic_ISBN
978-1-4244-4493-9
Type
conf
DOI
10.1109/IITC.2009.5090364
Filename
5090364
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