Title :
Chip-packaging interaction in Cu/very low-k interconnect
Author :
Wei, Hsiu-Ping ; Tsai, Hao-Yi ; Liu, Yu-Wen ; Chen, Hsien-Wei ; Jeng, Shin-Puu ; Yu, Douglas CH
Author_Institution :
Taiwan Semicond. Manuf. Co., Ltd. (TSMC), Hsinchu
Abstract :
Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is used to optimize the interconnect scheme from a packaging reliability point of view. Factors including top metal (or SiO2) thickness, passivation dielectric layers, and bump pad structure are found to play key roles in packaging process and reliability.
Keywords :
chip scale packaging; copper; finite element analysis; integrated circuit interconnections; reliability; Cu; bump pad structure; chip-packaging interaction; dielectric layers; multilevel finite element model; packaging reliability; passivation; top metal thickness; very low-k interconnect; Delamination; Dielectric films; Dielectric materials; Electronics packaging; Environmentally friendly manufacturing techniques; Equations; Finite element methods; Flip chip; Lead; Passivation;
Conference_Titel :
Interconnect Technology Conference, 2009. IITC 2009. IEEE International
Conference_Location :
Sapporo, Hokkaido
Print_ISBN :
978-1-4244-4492-2
Electronic_ISBN :
978-1-4244-4493-9
DOI :
10.1109/IITC.2009.5090366
