Si single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Author

Dae Hwan Kim ; Suk-Kang Sung ; Kyung Rok Kim ; Bum Ho Choi ; Sung Woo Hwang ; Doyeol Ahn ; Jong Duk Lee ; Byung-Gook Park

Author_Institution

Sch. of Electr. Eng., Seoul Nat. Univ., South Korea

fYear

2001

fDate

2-5 Dec. 2001

Abstract

Si single-electron transistors with sidewall depletion gates on a silicon-on-insulator nanowire are proposed and fabricated, using the combination of conventional lithography and process technology. The size dependence of device characteristics shows good controllability and reproducibility, and a dynamic multi-functional SET logic is successfully demonstrated at 10 K, for the first time.

Keywords

Coulomb blockade; elemental semiconductors; field effect logic circuits; lithography; logic gates; nanotechnology; silicon; silicon-on-insulator; single electron transistors; Si; controllability; device characteristics; dynamic multi-functional SET logic; dynamic single-electron transistor logic; lithography; process technology; reproducibility; sidewall depletion gates; silicon-on-insulator nanowire; single-electron transistors; size dependence; Amorphous materials; Controllability; Fabrication; Lithography; Logic; Reproducibility of results; Silicon on insulator technology; Single electron transistors; Temperature dependence; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979454

Filename

979454